1. Field of the Invention
The invention relates generally to an array of flash EEPROM cells and in particular to an architecture for an array of flash EEPROM cells with page erase and negative voltage gate erase.
2. Prior Art
Flash electrically erasable programmable read-only memory (EEPROM) has recently emerged as an important nonvolatile memory which combines the advantages of EPROM density with EEPROM electrical erasability. FIG. 1 illustrates a prior art cross-sectional view of an asymmetric flash EEPROM cell. Substrate 20, typically of P conductivity type, has a drain region 12 and a source region 10. Source region 10 consists of a shallow diffusion region 10A and a deeper diffusion region 10B. As used herein, "shallow" and "deep" refer to the distance into the substrate 20 from a selected surface of the substrate. Deep diffusion region 10B is typically formed using a phosphorous implant and shallow region 10A is typically formed using an arsenic implant after the phosphorous implant. Polysilicon gate 16 is separated from substrate 20 surface by a thin dielectric layer 15. Typically, dielectric layer 15 is silicon dioxide having a uniform thickness of about 100 .ANG.. Naturally, other dielectric layers could be used which have dielectric characteristics similar to the 100 .ANG. thick silicon dioxide layer.
Floating gate 16 has a first edge surface substantially aligned with shallow diffusion region 10A and a second edge surface, opposite to the first edge surface, overlying an edge surface of drain 12. A dielectric layer 17, separates control gate 18 from floating gate 16. A channel region 14 in substrate 20 separates source 10 and drain 12. The entire structure is overlaid by an oxide insulating layer 19 and means are provided for applying a source voltage V.sub.S through oxide layer 19 to source 10, a gate voltage V.sub.G to control gate 18, and a drain voltage V.sub.D through oxide layer 19 to drain 12.
To program the flash EEPROM cell of FIG. 1, drain 12 and control gate 18 are raised to predetermined potentials above the potential of source 10. For example, drain 12 has a voltage V.sub.D of about 5 volts while gate voltage V.sub.G is about 12 volts for approximately two to three milliseconds. These voltages produce "hot electrons" which are accelerated across gate dielectric 15 and onto floating gate 16. The hot electron injection results in an increase of the floating gate threshold by approximately 3 to 5 volts. This programming operation is similar to that of the typical EPROM cell.
To erase the flash EEPROM cell, drain 12 is floated. Control gate 18 is grounded and a voltage of about 12 volts is applied to the source for a few milliseconds. If an unprogrammed flash EEPROM cell in an array of such cells is repeatedly erased under these conditions, floating gate 16 acquires a more positive potential. Consequently, with control gate 18 grounded, eventually the cell is always on which in turn prevents reading of any other cell in the column of the array containing this cell. This condition is referred to as bit overerase.
The logical condition of the flash EEPROM cell is determined in a manner similar to the determination of the logical condition of an EPROM cell. Source 10 is held at ground potential and control gate 18 is held at a potential of about 5 volts. Drain 12 is held at a potential between one to two volts. Under these conditions, an unprogrammed cell conducts at a current level of between 25 to 50 microamps. A programmed cell does not conduct. For a more detailed discussion of an asymmetric flash EEPROM cell see for example, U.S. Pat. No. 4,698,787 issued on Oct. 6, 1987 to Mukherjee et al. which is incorporated herein by reference.
One embodiment of a prior art array 55 of flash EEPROM cells is illustrated in FIG. 2A. A multiplicity of flash EEPROM cells 30 are arranged in rows 60-1 to 60-M with each cell 30 in a row 60 being part of a column 70. (In the figures, similar components and/or features have the same reference label. The various components are distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used, the description is applicable to any one of the several similar components.) Within a column 70, the drains D of each cell are connected to a common bit line 51. The control gates in each row 60 are connected to a common word line 49. The sources S of all cells 30 are tied to a common source line 80.
This array configuration permits programming of individual cells 30. However, to erase any one cell, in array 55 requires that all of the cells in the array be erased. Specifically, common source line 80 is raised to a high potential level, the bit lines are floated, and all word lines 49 are held at a ground potential. The common connection of the sources of the memory cells in each row results in all cells being erased.
To erase smaller segments of flash EEPROM array 55, the array is subdivided into bytes as illustrated, for example, in FIG. 2B. In this embodiment, a select transistor 90 is added for each byte of array 55. To erase byte 1, word line 49-2 is brought high and all other word lines 49-1, 49-3 to 49-M are held low. All bit lines 51 are floated. Word line 49-2 turns transistor 90-2 on which results in a high voltage, typically 12 volts, on sources S of bytes 1 and 2. Since the gates of byte 2 are high, the cells in byte 2 are not affected, but the cells in byte 1 are erased.
However, this operation results in application of a high voltage to drains D of the cells connected to word line 49-3 and byte 1. Therefore, these cells experience a drain erase which is undesirable, because these cells must be reprogrammed to restore the stored information. Moreover, drain D is not a double diffusion and the high reverse bias voltage may result in breakdown of the junction.
The disruption of the row of cells connected to word line 49-3 is not the only problem associated with the erasure of byte 1. The high voltage on word line 49-2 drives the control gates in byte 4 high. This high voltage increases the charge on the floating gates in the cells in byte 4. Hence, the erasure of byte 1 results in a slow program of byte 4. This effect is referred to as a "gate disturb" of byte 4. In addition, the application of intermediate voltage to the other-decoded sources in byte 1 results in a slow erase of byte 3. Finally, the inherent resistance of transistor 90-1 results in slower programming of byte 1. Moreover, the array in FIG. 2B is large in comparison to the array in FIG. 2A so that arrays using byte selection are expensive.
With the array configuration of FIG. 2B, any row of the array could selectively be erased, if the row was defined as the byte. However, the various problems described above, with this architecture clearly limit the functionality of the array. Therefore, this architecture with a high voltage source erase does not provide a reasonable means for selectively programming and erasing a row of the array.
Alternatively, with the common source connection of FIG. 2A, a column at a time can be erased by applying about 20 volts on bit line 51, grounding word lines 49 and allowing common source line 80 to float or alternatively, grounding line 80. This configuration is referred to as a drain erase. However, as shown in FIG. 3, the number of cycles for a cell erased at a drain is only about 100 so that drain erasure significantly limits the endurance of the cell. Again, since the drain is not formed by a double diffusion, the high voltage on the drain is likely to result in breakdown of the junction.
Accordingly, a flash EEPROM array can selectively erase either a byte, a column, a row or the entire array. Drain erasure of columns limits the endurance of the device and may result in junction breakdown. The erasure of a row results in at least the erasure of another row. The erasure of the entire array limits the flexibility of operation of the flash EEPROM array in comparison to EPROM and EEPROM arrays. Therefore, a means for selectively erasing a predetermined number of rows within a flash EEPROM array while desirable is not currently available.